Test Series - computer fundamental

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Test Number 28/95

Q: What is the high speed memory between the main memory and the CPU called?
A. Register Memory
B. Cache Memory
C. Storage Memory
D. Virtual Memory
Solution: It is called the Cache Memory. The cache memory is the high speed memory between the main memory and the CPU.
Q: Cache Memory is implemented using the DRAM chips.
A. True
B. False
C. none
D. ...
Solution: The Cache memory is implemented using the SRAM chips and not the DRAM chips. SRAM stands for Static RAM. It is faster and is expensive.
Q: Whenever the data is found in the cache memory it is called as _________
A. HIT
B. MISS
C. FOUND
D. ERROR
Solution: Whenever the data is found in the cache memory, it is called as Cache HIT. CPU first checks in the cache memory since it is closest to the CPU.
Q: LRU stands for ___________
A. Low Rate Usage
B. Least Rate Usage
C. Least Recently Used
D. Low Required Usage
Solution: LRU stands for Least Recently Used. LRU is a type of replacement policy used by the cache memory.
Q: When the data at a location in cache is different from the data located in the main memory, the cache is called _____________
A. Unique
B. Inconsistent
C. Variable
D. Fault
Solution: The cache is said to be inconsistent. Inconsistency must be avoided as it leads to serious data bugs.
Q: Which of the following is not a write policy to avoid Cache Coherence?
A. Write through
B. Write within
C. Write back
D. Buffered write
Solution: There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.
Q: Which of the following is an efficient method of cache updating?
A. Snoopy writes
B. Write through
C. Write within
D. Buffered write
Solution: Snoopy writes is the efficient method for updating the cache. In this case, the cache controller snoops or monitors the operations of other bus masters.
Q: In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
A. Associative
B. Direct
C. Set Associative
D. Indirect
Solution: This happens in the associative mapping. In this case, a block of data from the main memory can be mapped anywhere in the cache memory.
Q: The number of sign bits in a 32-bit IEEE format is ____
A. 1
B. 11
C. 9
D. 23
Solution: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.
Q: The transfer between CPU and Cache is ______________
A. Block transfer
B. Word transfer
C. Set transfer
D. Associative transfer
Solution: The transfer is a word transfer. In the memory subsystem, word is transferred over the memory data bus and it typically has a width of a word or half-word.

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